1. Field of the Invention
The present invention relates generally to input circuits and more particularly relates to an input circuit for a charge transfer device which is used as a shift register, a delay element, a memory and so on.
2. Description of the Prior Art
An example of a conventional input circuit including a CCD (charge coupled device) when the CCD is used as a charge transfer element is shown in FIG. 1.
The example of FIG. 1 is the case in which a 2-phase n-channel CCD 1 of buried channel type is used. In this case, under the surface of a P type substrate 2 is formed an N and N.sup.- type diffusion layer 3, while over the surface of the P type substrate 2 are alternately deposited transfer electrodes to which control signals .phi..sub.1 and .phi..sub.2 are applied through an insulating layer (SiO.sub.2 layer or the like) 4. An N type diffusion layer 5 receives an input, and between layer 5 and a transfer area or section 6 are deposited input gates which are connected to terminals IG.sub.1 and IG.sub.2.
When an input signal (digital signal) is supplied to such CCD 1 according to a voltage input method, there is generally employed an input circuit 10 as, for example, shown in FIG. 1. More particularly, a transfer clock pulse P.sub.2 as shown in FIG. 2C is supplied to the first input gate electrode terminal IG.sub.1 and a fixed bias V.sub.G from a bias source 7 is supplied to the second input gate electrode terminal IG.sub.2. Also, a digital input signal S.sub.I shown in FIG. 2A is supplied to the input source layers from a signal source 8.
Accordingly, when the input signal S.sub.I (digital signal which alternately becomes "1" and "0" as shown in FIG. 2A) is taken in by the use of the transfer clocks (each having the frequency, for example, four times the subcarrier frequency) P.sub.1 and P.sub.2 shown in FIGS. 2B and 2C, a relation between potential wells (boundary surface potentials) formed by the transfer clocks P.sub.1 and P.sub.2 and the signal charge becomes as shown in FIG. 3.
FIG. 3B shows such relation between the potential well and the signal charge at time point t.sub.1 in FIG. 2. At time point t.sub.2, the accumulation or taken-in of a signal charge Q (shown by hatched area) is completed (FIG. 3C) and then from time point t.sub.3 the transfer of the signal charge Q is started (FIG. 3D).
The above potential well may sometimes be slightly displaced from a predetermined value due to scattering in the manufacturing process of the CCD 1. In this case, it is general that the displacement is different between the potential wells in the transfer section 6 and those at the input gate terminal IG. For example, when the potential well at the input gate terminal IG is displaced so as to become deeper by .DELTA.PW, the potential well in the transfer section 6 is displaced so as to become shallower by .DELTA.PW' (not always equal to the .DELTA.PW) as shown in FIG. 3C. When the potential well is considerably scattered in the process treatment of the CCD 1, the signal charge Q may frequently be overflowed during the transfer mode.
The reason for this is as follows. In general, in order to raise the S/N (signal-to-noise) ratio, the signal charge Q is taken in by a charge amount immediately before being overflowed under the normal transfer state, so that when the potential well becomes shallow by .DELTA.PW' as described above, although the taken-in charge amount is increased by .DELTA.Q, the transfer charge amount to be handled is decreased by .DELTA.Q'. As a result, the overflow of the signal charge Q is easily caused. The overflow of the signal charge causes a bit error to occur.
The overflow of the signal charge is caused by not only the scattering of the process treatment but also the fluctuation of the potential level due to the secular variation upon use and the fluctuation of the voltage V.sub.G which is supplied to the second input gate electrode terminal IG.sub.2. That is, when, for example, the bias voltage V.sub.G is changed, the potential level is changed, increasing the depth of the potential well more than the predetermined value.
Such defect can be removed if the input signal is taken in with the charge preset input method. FIG. 4A shows an example of an input circuit 10 which carries out the above charge preset input method. FIGS. 4B to 4D are respectively diagrams used to explain a relation between a potential well and a signal charge in the same way as in FIG. 3.
In this example, an inverted transfer clock P.sub.2 biased by voltage V.sub.S from a bias source 9 is supplied to an input source electrode terminal IS.sub.0 and a bias voltage V.sub.G is supplied to a first input gate electrode terminal IG.sub.1. And, an input signal S.sub.I is supplied between the first input gate electode terminal IG.sub.1 and a second input gate electrode terminal IG.sub.2.
As a result, a depth PW.sub.0 of the potential barrier formed within the region of the input gate IG, namely, potential well formed beneath the second input gate connected to electrode terminal IG.sub.2 is determined by the magnitude of the level of the input signal S.sub.I. Thus, when the scattering exists in the process treatment and therefore the potential level in the second input gate connected to electrode terminal IG.sub.2 becomes deeper by .DELTA.PW, the potential level in the first input gate electrode IG.sub.1 becomes deeper similarly by .DELTA.PW. In consequence, the depth PW.sub.0 of the potential barrier within the input gate region, or the potential well does not change at all.
Therefore, the charge amount Q to be taken in the potential well in the second input gate connected to electrode terminal IG.sub.2 is constant at all times. When the bias voltage V.sub.G is changed, the potential level in the first input gate connected to electrode terminal IG.sub.1 is changed. In this case, however, the input signal S.sub.I is supplied between the first and second input gate through electrode terminals IG.sub.1 and IG.sub.2 so that a relative level difference therebetween is constant as long as the level of the input signal S.sub.I is constant. Thus, the depth PW.sub.0 of the potential well is not changed by the bias voltage V.sub.G.
As described above, if the input signal S.sub.I is taken in according to the charge preset input method, even when the process treatment is scattered and the bias voltage V.sub.G provided in the input circuit 10 is fluctuated, the signal charge amount Q to be taken in is not changed so that the probability of overflow is reduced significantly.
However, in this input circuit 10, when the input signal S.sub.I is superimposed upon the bias voltage V.sub.G and then applied to the second input gate connected to electrode terminal IG.sub.2, a mixer 11 shown in FIG. 5 is used to couple the bias voltage V.sub.G with the input signal S.sub.I. When the mixer 11 is employed, by the integral action of a coupling capacitor C and a resistor R used therein, the potential at the second input gate connected to electrode terminal IG.sub.2 may sometimes be displaced to either V.sub.G or V.sub.G +V.sub.I (V.sub.I represents the level of the input signal S.sub.I).
The reason for this is that when, for example, "0" is inputted in succession in the signal series of the digital input signal S.sub.I, the integral action of the coupling capacitor C and the resistor R causes the potential at the second input gate connected to electrode terminal IG.sub.2 to become close to the bias voltage V.sub.G as shown in FIG. 6.
In consequence, the input circuit 10 shown in FIG. 4 inevitably requires a clamping circuit 12 shown in FIG. 7 and hence the construction of the input circuit 10 becomes complicated. Moreover, with the circuitry thus made, unless the fixed bias V.sub.S is applied to the first input gate connected to electrode terminals IG.sub.1, the potential level as shown in FIG. 4B can not be obtained so that two bias sources 7 and 9 are indispensable therefor.